![Does anyone know why this VHDL code is not counting on my FPGA? The 7-segment is stuck on "0". So I am assuming it is not making it to the second count Does anyone know why this VHDL code is not counting on my FPGA? The 7-segment is stuck on "0". So I am assuming it is not making it to the second count](https://preview.redd.it/does-anyone-know-why-this-vhdl-code-is-not-counting-on-my-v0-3uju1j6xm64a1.png?auto=webp&s=9095f5907457c3b788d495474164595aab1403e7)
Does anyone know why this VHDL code is not counting on my FPGA? The 7-segment is stuck on "0". So I am assuming it is not making it to the second count
![VHDL for FPGA Design/State-Machine Design Example Asynchronous Counter - Wikibooks, open books for an open world VHDL for FPGA Design/State-Machine Design Example Asynchronous Counter - Wikibooks, open books for an open world](https://upload.wikimedia.org/wikipedia/commons/thumb/5/5c/Asynchronous_Counter.pdf/page1-1275px-Asynchronous_Counter.pdf.jpg)
VHDL for FPGA Design/State-Machine Design Example Asynchronous Counter - Wikibooks, open books for an open world
![L18 – VHDL for other counters and controllers. Other counters More examples Gray Code counter Controlled counters Up down counter Ref: text Unit. - ppt download L18 – VHDL for other counters and controllers. Other counters More examples Gray Code counter Controlled counters Up down counter Ref: text Unit. - ppt download](https://images.slideplayer.com/15/4548800/slides/slide_5.jpg)